We propose a basic research project that is aimed at utilizing and deepening the current results of three research groups in the field of on-line and off-line testing and diagnostics with the intension to utilize them in the design of fault tolerant systems. The fault tolerant methodologies will be developed on three levels: level of error tolerance, level of single-event upset detection with additional reconfiguration and a level of system architecture graceful degradation in case of unrecoverable faults appearance. The goal of this project is to design a new, advanced design methodology for fault-tolerant circuits that will be based on the new technological possibilities.

Description in Czech
We propose a basic research project that is aimed at utilizing and deepening the current results of three research groups in the field of on-line and off-line testing and diagnostics with the intension to utilize them in the design of fault tolerant systems. The fault tolerant methodologies will be developed on three levels: level of error tolerance, level of single-event upset detection with additional reconfiguration and a level of system architecture graceful degradation in case of unrecoverable faults appearance. The goal of this project is to design a new, advanced design methodology for fault-tolerant circuits that will be based on the new technological possibilities.

Keywords
fault tolerant systems, dependability

Key words in Czech
systémy odolné proti poruchám, spolehlivost

GA102/09/1668

English

Kotásek Zdeněk, doc. Ing., CSc. - principal person responsible

Department of Computer Systems
- responsible department (11.3.2009 - not assigned)
Faculty of Information Technology
- responsible department (13.5.2011 - not assigned)
Dependable Digital Systems Research Group
- internal (11.3.2009 - 31.12.2011)
Faculty of Information Technology
- co-beneficiary (1.1.2009 - 31.12.2011)
Faculty of Information Technology
- beneficiary (13.5.2011 - not assigned)

BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. p. 108-108. ISBN: 978-80-214-4305-1.
Detail

MIČULKA, L. Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA. Počítačové architektury & diagnostika 2011. Bratislava: Fakulta informatiky a informačních technologií Slovenská technická univerzita v Bratislavě, 2011. s. 61-66. ISBN: 978-80-227-3552-0.
Detail

BARTOŠ, P. Test Time Reduction by Scan Chain Reordering. Proceedings of the 17th Conference STUDENT EEICT 2011. Volume 3. Brno: Faculty of Electrical Engineering and Communication BUT, 2011. p. 564-568. ISBN: 978-80-214-4273-3.
Detail

STRNADEL, J. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: Technical University Wien, 2011. p. 29-32.
Detail

RŮŽIČKA, R.; ŠIMEK, V. Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles. Proceedings of 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011. p. 205-212. ISBN: 978-0-7695-4494-6.
Detail

BARTOŠ, P. Metody optimalizace propojení scan řetězce. Počítačové architektury a diagnostika 2011. Bratislava: Vydavateľstvo STU, 2011. s. 97-102. ISBN: 978-80-227-3552-0.
Detail

STRNADEL, J. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011. p. 21-22. ISBN: 978-3-902457-30-1.
Detail

RUMPLÍK, M.; STRNADEL, J. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011. p. 367-374. ISBN: 978-0-7695-4494-6.
Detail

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011. p. 223-230. ISBN: 978-0-7695-4494-6.
Detail

BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 371-374. ISBN: 978-1-4244-9753-9.
Detail

STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 397-398. ISBN: 978-1-4244-9753-9.
Detail

ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. 142 s. ISBN: 978-80-214-4209-2.
Detail

BARTOŠ, P.; KOTÁSEK, Z.: ScanOpt; Tool for scan chain routability visualisation, analysis and optimization. https://wis.fit.vutbr.cz/FIT/db/vav/view_product.php?id=169. URL: https://wis.fit.vutbr.cz/FIT/db/vav/view_product.php?id=169. (software)
Detail

STRNADEL, J. Návrh časově kritických systémů I: specifikace a verifikace. Automa, 2010, roč. 2010, č. 10, s. 42-44. ISSN: 1210-9592.
Detail

KOTÁSEK, Z.; STRAKA, M. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, 2009, vol. 2009, no. 3, p. 8-15. ISSN: 1335-8243.
Detail

KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 364-369. ISBN: 978-1-4244-6610-8.
Detail

KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010. p. 644-651. ISBN: 978-0-7695-4171-6.
Detail

ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274. Berlin: Springer Verlag, 2010. p. 181-192. ISBN: 978-3-642-15322-8. ISSN: 0302-9743.
Detail

STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Design of Highly Dependable Systems in FPGA. International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010. p. 186-193. ISBN: 978-80-8086-164-3.
Detail

FIŠER, P.; SCHMIDT, J.; VAŠÍČEK, Z.; SEKANINA, L. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 346-351. ISBN: 978-1-4244-6610-8.
Detail

Responsibility: Kotásek Zdeněk, doc. Ing., CSc.