Publication detail

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

RUMPLÍK, M. STRNADEL, J.

Original Title

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is detected between RTL testability analysis results and low-level test pattern generation results. In the paper, it is shown such a correlation exists although relatively simple academic RTL testability analysis solution is compared to widely used commercial gate-level test pattern generation solution. Detail results achieved during the experiments over scan circuits are presented, discussed and summarized in the paper.

Keywords

testability, fault coverage, stuck at fault, register transfer level, correlation, scan, digital, circuit

Authors

RUMPLÍK, M.; STRNADEL, J.

RIV year

2011

Released

30. 8. 2011

Publisher

IEEE Computer Society

Location

Oulu

ISBN

978-0-7695-4494-6

Book

Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011

Pages from

367

Pages to

374

Pages count

8

URL

BibTex

@inproceedings{BUT76344,
  author="Michal {Rumplík} and Josef {Strnadel}",
  title="On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits",
  booktitle="Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011",
  year="2011",
  pages="367--374",
  publisher="IEEE Computer Society",
  address="Oulu",
  isbn="978-0-7695-4494-6",
  url="http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6037434"
}