Decreasing Test Time by Scan Chain Reorganization

Decreasing Test Time by Scan Chain Reorganization

Paper in proceedings outside WoS and Scopus

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

scan chain, test, time, reordering, reorganization, physical, layout

scan chain, test, time, reordering, reorganization, physical, layout

BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J.

2012

13.04.2011

IEEE Computer Society

Cottbus

978-1-4244-9753-9

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

371

374

4

ddecs2011_Bartos