Publication result detail

The Design of On-line Checkers and Their Use in Verification and Testing

KOTÁSEK, Z.; STRAKA, M.

Original Title

The Design of On-line Checkers and Their Use in Verification and Testing

English Title

The Design of On-line Checkers and Their Use in Verification and Testing

Type

Peer-reviewed article not indexed in WoS or Scopus

Original Abstract

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

English abstract

In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.

Keywords

on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA

Key words in English

on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA

Authors

KOTÁSEK, Z.; STRAKA, M.

RIV year

2011

Released

01.09.2009

ISBN

1335-8243

Periodical

Acta Electrotechnica et Informatica

Volume

2009

Number

3

State

Slovak Republic

Pages from

8

Pages to

15

Pages count

8

BibTex

@article{BUT47975,
  author="Zdeněk {Kotásek} and Martin {Straka}",
  title="The Design of On-line Checkers and Their Use in Verification and Testing",
  journal="Acta Electrotechnica et Informatica",
  year="2009",
  volume="2009",
  number="3",
  pages="8--15",
  issn="1335-8243"
}