This dissertation confronts the dual challenges of securing high-speed networks and preparing for the quantum computing era. Traditional software cryptography fails to perform at line rates of 100 Gbps, while established public-key algorithms are vulnerable to quantum attacks. This work presents the design, implementation, and empirical validation of a holistic, hardware-accelerated cryptographic system on Field-Programmable Gate Arrays (FPGAs) as a solution.

The research progressed from the ground up, beginning with the development of highly-optimized hardware primitives in VHDL (VHSIC Hardware Description Language). High-performance cores were developed for the quantum-resistant AES-256-GCM (Galois-Counter Mode) cipher and the new National Institute of Standards and Technology (NIST) post-quantum standards: ML-KEM (CRYSTALS-Kyber) for key encapsulation and ML-DSA (CRYSTALS-Dilithium) for digital signatures. The subsequent challenge was integrating these isolated components into a cohesive architecture. This culminated in the dissertation's primary contribution: a holistic traffic encryptor. The system's core innovation is a sophisticated hybrid key management mechanism that securely combines keys from classical (Elliptic Curve Diffie-Hellman - ECDH), post-quantum (ML-KEM), and quantum (Quantum Key Distribution - QKD) sources to generate a single, robust session key.

To prove its real-world viability, the final architecture was implemented in two distinct models: a high-performance hardware version for network gateways and a compatible software version for less powerful end-devices. The entire system was rigorously validated through empirical testing, which included a long-distance international pilot and high-speed lab benchmarks. These tests confirmed the hardware's ability to provide robust, end-to-end security at line rates up to 100 Gbps.