FIT-ACHAcad. year: 2018/2019
The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on SIMD streaming instructions and on graphical processors (SIMT). Parallelization of numerical calculations for GPU is also covered (CUDA). Techniques of low-power processors are also explained.
Learning outcomes of the course unit
Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. Get acquainted with processor performance measurement. The knowledge of architecture and hardware support of parallel computation on graphic processors can be directly applied for acceleration of intensive calculations.
Von Neumann computer architecture, memory hierarchy, programming in assembly language, compiler's tasks and functions
Recommended optional programme components
Recommended or required reading
current PPT slides for lectures
Agner Fog: Software optimization resources
Intel Architecture Optimization Manual
Nvidia CUDA SDK Manual
Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1
Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 493 s., ISBN: 978-0-12-383872-8
Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
Jeffers, J., and Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 2013, Morgan Kaufmann, p. 432), ISBN: 978-0-124-10414-3
Planned learning activities and teaching methods
Assesment methods and criteria linked to learning outcomes
Assessment of two projects, 13 hours in total and, computer laboratories and a midterm examination.
To get 20 out of 40 points for projects and midterm examination.
Language of instruction
To familiarize students with architecture of the newest processors exploiting the instruction-level, thread-level and data-level parallelism. To clarify the role of a compiler and its cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical processors and its use for acceleration of numerical calculations (GPGPU), and with low-power techniques in processors for mobile applications.
Specification of controlled education, way of implementation and compensation for absences
- Missed labs can be substituted in alternative dates (monday or friday)
- There will be a place for missed labs in the last week of the semester.
Classification of course in study plans
- Programme IT-MGR-2 Master's
branch MBI , any year of study, winter semester, 5 credits, elective
branch MIS , any year of study, winter semester, 5 credits, elective
branch MBS , any year of study, winter semester, 5 credits, compulsory-optional
branch MIN , any year of study, winter semester, 5 credits, elective
branch MMM , any year of study, winter semester, 5 credits, elective
branch MPV , 2. year of study, winter semester, 5 credits, compulsory
branch MGM , 2. year of study, winter semester, 5 credits, elective
branch MSK , 2. year of study, winter semester, 5 credits, compulsory-optional
Type of course unit
26 hours, optionally
Teacher / Lecturer
- Scalar processors. Pipelined instruction processing and compiler asistance
- Superscalar CPU. Dynamic instruction scheduling, branch prediction.
- Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
- Optimization of instruction and data fetching. Examples of superscalar CPUs.
- Multi-threaded processors.
- Data parallelism. SIMD extensions and vectorization.
- Architecture of graphics processing units, SIMT programming model.
- CUDA programming language, thread and memory model.
- Synchronisation and reduction on GPU, design and tuning of GPU codes.
- Stream processing, multi-GPU systems, GPU libraries.
- Architecture of many core systems (MIC, Xeon Phi) and their programming.
- VLIW processors. SW pipelining, predication, binary translation.
- Low power processors.
Exercise in computer lab
10 hours, compulsory
Teacher / Lecturer
- Performance measurement for sequential codes.
- Vectorisation using OpenMP 4.0.
- CUDA: Memory transfers, simple kernels.
- CUDA: Shared memory.
- CUDA: Texture and constant memory, reduction operation.