Course detail

Programmable Logic Devices

FEKT-MPLDAcad. year: 2011/2012

The course is aimed to extend the knowledge of digital technique. Types of programmable devices: SPLD, CPLD and FPGA devices. Special function blocks used in PLD devices. Text description (HDL languages) and graphical description of PLD subsystems. CAD development systems and their use for simulation of digital subsystems (combinational circuits, counters, state machines), synthesis and implementation into CPLD and FPGA devices. Functional verification of designed subsystems by programming laboratory kits.

Language of instruction

Czech

Number of ECTS credits

6

Mode of study

Not applicable.

Guarantor

Ing. Michal Kubíček, Ph.D.

Department

Department of Radio Electronics (UREL)

Learning outcomes of the course unit

Students acquire survey of the programmable logic device types and of their use in digital design. They become familiar with development systems and with their use for description, synthesis, implementation and simulation of digital systems.

Prerequisites

Knowledge of digital design on the Bachelor´s degree level is requested.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Teaching methods depend on the type of course unit as specified in the article 7 of BUT Rules for Studies and Examinations.

Assesment methods and criteria linked to learning outcomes

The computer exercises and result of the final examination are evaluated.

Course curriculum

Technology of integrated circuits, ASSP, ASIC, Structured ASIC, PLD.
Architecture of FPGAs, FPGA on the market, future of FPGAs.
Using microcontrollers and other advanced features of FPGAs (gigabit transceivers, MAC, PCI-Express), system on chip (SoC).
VHDL basics, typical coding examples, IP cores and its usage.
Verification: testbench, behavioral simulation, post PAR simulation.
Design of PLD-based systems: power, signal integrity, packing, PCB.

Work placements

Not applicable.

Aims

The aim of the course is extension of knowledge of digital technique, especially of programmable logic devices and FPGAs. Students learn how to use these devices in their digital designs in diploma projects and in practice.

Specification of controlled education, way of implementation and compensation for absences

The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

KOLOUCH, J.: Programovatelné logické obvody - přednášky. [Skriptum FEKT VUT v Brně.] MJ servis, Brno 2005 (CS)
KOLOUCH, J.: Programovatelné logické obvody a návrh jejich aplikací v jazyku VHDL - počítačové cvičení. [Skriptum FEKT VUT v Brně.] MJ servis, Brno 2005 (CS)

Recommended reading

WAKERLY, J.: Digital Design - principles and practices. 4-th Ed. Pearson Education LTD, Prentice Hall, 2005 (EN)

Classification of course in study plans

  • Programme EEKR-M Master's

    branch M-TIT , 1. year of study, summer semester, optional interdisciplinary
    branch M-EST , 1. year of study, summer semester, optional specialized
    branch M-MEL , 2. year of study, summer semester, optional interdisciplinary
    branch M-SVE , 2. year of study, summer semester, optional interdisciplinary

  • Programme EEKR-CZV lifelong learning

    branch ET-CZV , 1. year of study, summer semester, optional specialized

Type of course unit

 

Lecture

26 hours, optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Survey of ways how to implement digital systems. Logic functions, their realization in PROM, PAL, PLA structures . ASSP and ASIC devices.
Simple PLDs, their functional blocks, macrocells of GAL 16V8 and 20V8 devices. Other SPLD types, their labelling and parameters
Complex PLD and FPGA devices - structure, basic properties
Introduction to VHDL programming language, synthesis and implementation (translation, mapping, place and route), constraints
Asynchronous (combinational) and synchronous (sequence) logic systems in PLDs.
Counters: binary, decimal (one- and bidirectional, with shortened cycle), Gray counter, LFSR – properties, HDL description
State machines (SM): Moore and Mealy type, HDL description, their compilation to SOP form
Simplifying of SM - equivalent states, their finding. State coding for PLDs and FPGAs. Algorithmic description of SM
Timing in programmable devices, pipelining, register retiming. Metastability, usage of reset signal and corresponding HDL description
FPGA devices - additional blocks: I/O standards, memory elements, blocks for frequency synthesis and for further handling of clock signals, fast serial communication, DSP blocks
Implementation of processors, use of intellectual property blocks
Boundary scan, PLD configuration, PCB design for PLD.

Exercise in computer lab

39 hours, compulsory

Teacher / Lecturer

Ing. Libor Boleček, Ph.D.
Ing. Michal Kubíček, Ph.D.
Ing. Pavel Štraus

Syllabus

Introduction to VHDL and ISE design tool
Basic functions, combinational logic (decoding)
Hierarchical design, usage of schematic
Implementation of sequential systems (counters)
State machines and their VHDL description
Structural description, testbench, simulation
LFSR counter, timing parameters, power consumption of FPGA
Usage of IP cores
Usage of ChipScope tool
Microprocessors in FPGA - PicoBlaze, MicroBlaze