Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

Paper in proceedings (conference paper)

The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

Simulation, Software data recovery, VHDL-AMS

Simulation, Software data recovery, VHDL-AMS

KUBÍČEK, M.

01.01.2007

MJ servicsBožetěchova 133, 612 00 Brno, Czech Republic

Department of Radio Electronics, Brno University of TechnologyPurkyňova 118, 612 00 Brno, Czech Republic

978-1-4244-0821-4

Proceedings of 17th International Conference Radioelektronika 2007

211

214

4

http://hdl.handle.net/