Publication results

• 2025

  PIŇOS, M.; KLHŮFEK, J.; MRÁZEK, V.; SEKANINA, L. Inference Energy Analysis in Context of Hardware-Aware NAS. In 2025 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Lyon: Institute of Electrical and Electronics Engineers, 2025. p. 161-164. ISBN: 979-8-3315-2801-0.
  Detail

  KLHŮFEK, J.; MARCHISIO, A.; MRÁZEK, V.; SEKANINA, L.; SHAFIQUE, M. TransInferSim: Toward Fast and Accurate Evaluation of Embedded Hardware Accelerators for Transformer Networks. IEEE Access, 2025, vol. 13, no. October, p. 177215-177226.
  Detail

  SEDLÁK, D.; KLHŮFEK, J.; MRÁZEK, V.; VAŠÍČEK, Z. Towards Efficient Scheduling of Transformer Neural Network Computation for Edge AI Deployment. Proceedings of the Genetic and Evolutionary Computation Conference Companion. Malaga: Association for Computing Machinery, 2025. p. 2242-2248. ISBN: 979-8-4007-1464-1.
  Detail

• 2024

  KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024. p. 1-6. ISBN: 979-8-3503-5934-3.
  Detail

• 2022

  KLHŮFEK, J.; MRÁZEK, V. ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague: Institute of Electrical and Electronics Engineers, 2022. p. 44-47. ISBN: 978-1-6654-9431-1.
  Detail

*) Citations are generated once every 24 hours.