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Bachelor's Thesis
Author of thesis: Jáchym Kutík
Acad. year: 2025/2026
Supervisor: doc. Ing. Lukáš Fujcik, Ph.D.
Reviewer: Ing. Vojtěch Dvořák, Ph.D.
This bachelor’s thesis deals with the design and implementation of a Direct Memory Access (DMA) controller compliant with the AMBA AHB-Lite bus protocol. The objec- tive is to develop an efficient hardware module that offloads routine data transfer tasks from the central processing unit (CPU), thereby increasing overall system throughput. The DMA controller is designed with support for cycle stealing transfer mode, multi- channel operation, and store-and-forward (S&F) mechanism. The design is implemented in SystemVerilog and verified using a UVM-based framework testbench.
DMA, AHB-Lite, SystemVerilog, UVM, Verification, RTL
Date of defence
16.06.2026
Result of the defence
Defended (thesis was successfully defended)
Grading
A
Process of defence
Student seznámil státní zkušební komisi s řešením své bakalářské práce. Zodpověděl otázky a připomínky oponenta. Dále odpověděl otázky komise:
Language of thesis
English
Faculty
Fakulta elektrotechniky a komunikačních technologií
Department
Department of Microelectronics
Study programme
Microelectronics and Technology (BPC-MET)
Composition of Committee
doc. Ing. et Ing. Pavel Šteffan, Ph.D. (předseda) doc. Ing. Vítězslav Novák, Ph.D. (místopředseda) Ing. Michal Pavlík, Ph.D. (člen) Ing. Vojtěch Dvořák, Ph.D. (člen) Ing. Michal Jelínek, Ph.D. (člen)
Supervisor’s reportdoc. Ing. Lukáš Fujcik, Ph.D.
Grade proposed by supervisor: A
Reviewer’s reportIng. Vojtěch Dvořák, Ph.D.
Grade proposed by reviewer: A
Responsibility: Mgr. et Mgr. Hana Odstrčilová