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Master's Thesis
Author of thesis: Ing. Erik Voda
Acad. year: 2025/2026
Supervisor: Ing. Vojtěch Král
Reviewer: Ing. Jiří Šolc
This master's thesis focuses on the optimization and evaluation of flip-flop topologies for standard-cell design. Static, dynamic, semi-dynamic, sense-amplifier-based, and single-phase-clocked flip-flops are compared. The aim is to evaluate their behavior in terms of power consumption, leakage current, timing parameters, area, and reliability. An automated simulation-based optimization framework was created for the pre-layout evaluation. The framework generates transistor sizing candidates, prepares netlists, runs ELDO simulations, extracts the required metrics, and uses Differential Evolution to guide the optimization process. Selected topologies were then implemented as physical layouts in Cadence Virtuoso. After parasitic extraction using the PEX flow with xACT 3D RCC settings, post-layout simulations were performed. Reliability simulations were also included to evaluate the effect of transistor aging on leakage current, power consumption, and clock-to-output delay. The results show that no topology is optimal for all design targets. After layout extraction and aging evaluation, the 18TSPC topology achieved the best overall trade-off. MTGFF remained a robust reference topology, while SAFF, SDFF, and ACFF showed advantages for more specific design goals.
flip-flop topologies, standard-cell design, transistor-level optimization, Differential Evolution, ELDO simulation, parasitic extraction, CMOS reliability, transistor aging
Date of defence
09.06.2026
Result of the defence
Defended (thesis was successfully defended)
Grading
A
Process of defence
Student seznámil státní zkušební komisi s řešením své diplomové práce. Zodpověděl otázky a připomínky oponenta. Dále odpověděl otázky komise: V Prezentaci jsi pracoval s časovými proměnnými TCQ, deltaTCQ. Interpretujte tyto veličiny. Čím je rozdíl v klopných obvodech způsoben. Můžete říct, jaká z Vašich buněk byla použita ve standartní knihovně a v jakém technologickém modu? Proč jste nepoužil ostatní layouty v programu? Layouty jste dělal sám?
Language of thesis
English
Faculty
Fakulta elektrotechniky a komunikačních technologií
Department
Department of Microelectronics
Study programme
Microelectronics (MPC-MEL)
Composition of Committee
doc. Ing. František Urban, CSc. (předseda) prof. Ing. Jaromír Hubálek, Ph.D. (místopředseda) doc. Ing. Juraj Marek, Ph.D. (člen) Ing. Vladimír Levek, Ph.D. (člen) Ing. Jan Ludvík (člen) doc. Ing. Imrich Gablech, Ph.D. (člen)
Supervisor’s reportIng. Vojtěch Král
Grade proposed by supervisor: A
Reviewer’s reportIng. Jiří Šolc
Grade proposed by reviewer: A
Responsibility: Mgr. et Mgr. Hana Odstrčilová