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Bachelor's Thesis
Author of thesis: Matyáš Peštál
Acad. year: 2025/2026
Supervisor: Ing. Filip Wagner
Reviewer: Ing. Patrik Dobiáš
This bachelor thesis focuses on the design and hardware implementation of the ChaCha stream cipher on an FPGA platform using VHDL. The introductory section analyzes the theoretical foundations of the ChaCha algorithm, its security parameters, and a comparison with other modern stream ciphers. The core of the work consists of the actual implementation of a keystream generation component, which utilizes an iterative architecture with a single Quarter-round transformation unit to achieve efficient logic resource utilization. The designed hardware was synthesized on an Artix-7 chip, and its functionality was verified against reference vectors from the RFC 8439 standard.
ChaCha; stream cipher; ARX; FPGA; VHDL; cryptography; Hardware implementation; keystream; Artix-7; RFC 8439
Date of defence
16.06.2026
Result of the defence
Defended (thesis was successfully defended)
Grading
C
Process of defence
Student prezentoval výsledky své práce a komise byla seznámena s posudky. Student obhájil bakalářskou práci s výhradami a odpověděl na otázky členů komise a oponenta.
Language of thesis
Czech
Faculty
Fakulta elektrotechniky a komunikačních technologií
Department
Department of Telecommunications
Study programme
Information Security (BPC-IBE)
Composition of Committee
doc. Ing. Karel Burda, CSc. (předseda) JUDr. Ing. František Kasl, Ph.D. (místopředseda) RNDr. Ing. Pavel Šeda, Ph.D. (člen) Ing. Ľuboš Nagy, Ph.D. (člen) Ing. Vlastimil Člupek, Ph.D. (člen) Ing. Jan Pospíšil, Ph.D. (člen) Ing. Martin Plšek, Ph.D. (člen)
Supervisor’s reportIng. Filip Wagner
Grade proposed by supervisor: B
Reviewer’s reportIng. Patrik Dobiáš
Grade proposed by reviewer: C
Responsibility: Mgr. et Mgr. Hana Odstrčilová