Course detail

Programmable Logic Devices

FEKT-MPA-PLDAcad. year: 2026/2027

Students get more detailed knowledge in the area of digital circuits design, especially with respect to their implementation into FPGAs (or ASICs). Students get overview of current technology of these integrated circuits, their off-the-shelf architectures, principles of design and application of basic digital subsystems (counters, finite state machines, memory structures). During the PC lectures students get familiar with modern system for FPGA configuration. This includes description of the digital system (using VHDL source codes, schematic, IP cores), its implementation and verification using simulator. After passing the course students are able to design and implement simple digital system into an FPGA (using VHDL language).

Language of instruction

English

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

Ing. Michal Kubíček, Ph.D.

Department

Department of Radio Electronics (UREL)

Offered to foreign students

Of all faculties

Entry knowledge

Students are expected to know basic of impulse and digital technology: the Boolean algebra, Karnaugh maps, truth tables, function of basic gates and flip-flops (registers), principle and effect of signal propagation through active and passive transmission elements.

Rules for evaluation and completion of the course

Students are evaluated continuously during the semester for active work in computer exercises (36 b). At least 50% of the points in the computer exercises are required for credit. The compulsory final exam consists of a practical and an oral part (total 64 pts). In order to pass the exam, you must score at least 50% of the points in each scored activity.
Computer exercises are compulsory; absences must be made up by agreement with the instructor. Evaluation of activities is specified by a regulation, which is issued by the lecturer responsible for the course annually. 

Aims

Lectures are aimed to teach students the basic principles of FPGAs, while they will be able not only to configure (program) them, but also select proper device and implement it into a system.
The graduate is able to: (a) describe simple digital system using VHDL; (b) verify simple digital system using VHDL; (c) choose type of finite state machine and give reasons for the choice; (d) design and implement a finite state machine using VHDL; (e) compare different architectures of PLDs and choose a proper one for particular application; (f) specify timing requirements for a design and verify that they are met after implementation; (g) implement simple IP cores like memories and simple DSP blocks (FIR filtres); (h) implement simple microcontroller into FPGA, program it and use in target application; (i) state requirements on FPGA power supply system; (j) analyze and prevent/solve basic signal integrity issues.

Study aids

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Lindh, L., Klevin, T.: Advanced HW/SW Embedded System for Designers, FPGA - System On Chip. Independently published, 2018, ISBN: 978-1731115812 (EN)
Wilson, P.: Design Recipes for FPGAs: Using Verilog and VHDL, 2nd Edition. Newnes, 2018, ISBN: 978-0080971292 (EN)

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme MPAD-CAN Master's 1 year of study, summer semester, compulsory-optional
  • Programme MPAD-CAN Master's 1 year of study, summer semester, compulsory-optional
  • Programme MPA-NCP Master's 1 year of study, summer semester, compulsory-optional

Type of course unit

 

Lecture

26 hours, optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

1. Introductiona to digital integrated circuits, history and development of CPLDs and FPGAs. 2. Introduction to VHDL programming language. 3. The basics of digital systems: gates, flip-flops, shift registers, counters. 4. Theory of finite state machines, Moor and Mealy state machines. 5. Practical design and application of finite state machines, microsequencers. 6. Basis architecture of FPGAs and CPLDs: logic cells, programmable interconnect, I/O cells. 7. Timing of digital circuits, metastability, methods for increasing clock frequency. 8. FPGA clock domains, clock enabling, clock management, synchronous and asynchronous reset. 9. Memory structures in FPGAs, use of RAM, ROM and FIFO. 10. Digital signal processing in FPGAs, dedicated blocks for DSP acceleration. 11. Advanced FPGA structural features, HARD and SOFT IP cores, implementation of basic IP cores. 12. Processors in FPGA, SoC, FPGA manufacturing technology, FPGA configuration. 13. Signal integrity, PCB and power design for FPGA, radiation effects.

Exercise in computer lab

26 hours, compulsory

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

1. Introduction to VHDL and Vivado design system, constraints. 2. Simulation, verification, tetbench 3. Basic commands, implementation of combinational functions (decoders). 4. Using hierarchical description, structural description. 5. Implementation of sequential systems (counters). 6. Finite state machines, description in VHDL. 7. Digital signal processing, FIR filter. 8. LFSR counter, timing parameters of structures, FPGA consumption. 9. Using IP cores, timing closure. 10. Use of integrated logic analyzer. 11. Processors in FPGA - PicoBlaze, basic principle of use. 12. Processors in FPGA - PicoBlaze, custom peripherals. 13. Processors in FPGA - MicroBlaze.

Individual preparation for excercises

26 hours, optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Independent study of materials related to the exercise; preparation of calculations, designs, and procedures for practical tasks; study of instructions and technical documentation; continuous preparation for knowledge assessment.

  

Individual preparation for a final exam

60 hours, optionally

Teacher / Lecturer

Ing. Michal Kubíček, Ph.D.

Syllabus

Independent review and systematization of the topics covered during the semester; study of course materials; practice of theoretical knowledge and practical skills; solving sample tasks and comprehensive preparation for the final examination.