Course detail

Testování polovodičů a čipů

FEKT-MPC-TPCAcad. year: 2025/2026

    - Introduction, terms and definitions

    - Why do testing at all - yields, cost of testing, quality and reliability

    - The system-on-chip development process - process milestones, maturity phases, product life cycle testing, risk assessment

    - Design for testability - Economics and cost, defect and failure models, design techniques, scan design, boundary scan, ATPG, BIST, IDDQ test, memory test

    - Test development based on DSP, test hardware and software development

    - Production testing such as IC Backend production flow, test hall infrastructure, wafer testing and final testing, multi-site testing.

    Language of instruction

    Czech

    Number of ECTS credits

    Mode of study

    Not applicable.

    Guarantor

    prof. Ing. Jaromír Hubálek, Ph.D.

    Department

    Department of Microelectronics (UMEL)

    Entry knowledge

    The student should have a fundamental knowledge of analog and digital lectronic circuit design, fundamentals of circuit measurement, an overview of measurement methods and accuracy, fundamentals of statistics, fundamentals of control engineering and sampling systems. Generally required knowledge at the level of a bachelor's degree in electrical engineering.

    Work in the laboratory is subject to a valid "instructed person" qualification, which students must obtain before starting the course. Information on this qualification is given in the Dean's Guideline on Student Familiarity with Safety Regulations.  

    Rules for evaluation and completion of the course

    The definition of supervised teaching and the way it is carried out are set out in the annually updated decree of the course guarantor. 

     

    Aims

    Introduce students to the basic concepts of chip testing and diagnostics, why it is necessary to test, what is the system-on-chip design approach from a testing perspective including risks, how to design test systems and protocols, test automation, difference in testing analog and digital circuits, use of DSP, what is production testing.

    Upon successful completion of the course, the student will be familiar with the basic terminology, have an overview of concepts and methods of chip testing including integrated test structures. Understand the importance of design for test and good test development.  Understands the economics of testing and ramp-up process for successful products.

    Study aids

    Scriptum, presentations, handouts for exercises. All available in elearning.  

    Prerequisites and corequisites

    Not applicable.

    Basic literature

    Abramovici, Breuer, Friedman :Digital Systems Testing and Testable Design Wiley-IEEE Press , 1994 , ISBN 0-7803-1062-4 (EN)
    Bushnell, Agrawal : Essentials of Electronic Testing Springer US , 2nd ed. 2005 , ISBN 978-0-7923-7991-1 (EN)
    Kelly, Engelhardt: Advanced Testing of RF, SoC and SiP Devices Artech House, 2007, ISBN 10: 1-5805-3709-X (EN)
    Kelly, Schaub: Production Testing of RF and System-on-a-Chip Devices for Wireless Communications Artech House, Boston 2004, ISBN 10: 1-58-053-692-1 (EN)
    Lowe : The Fundamentals of Mixed Signal Testing Soft test Inc. , 1999 , ISBN 0-96-587-972-0 (EN)
    Mahoney : DSP-Based Testing of Analog and Mixed-Signal Circuits IEEE Number 785, 1987 , ISBN 0-8186-0785-8 (EN)
    Perry : The Fundamentals of Digital Semiconductor Testing Soft Test Inc. , 1999 , ISBN 0-9658797-0-4 (EN)
    Rajsuman : IDDQ Testing for CMOS VLSI Artech House , London 1995, ISBN 978-0-89-006-726-0 (EN)
    Rajsuman : System-on-a-Chip Design and Test Artech House , Boston, 2000 , ISBN 978-1-58053-107-8 (EN)
    Roberts : Metrics, Techniques and New Developments in Mixed-Signal Testing Tutorial held at ITC 1999 in Atlantic City (EN)
    Roberts; Taenzler; Burns : An Introduction to Mixed-Signal IC Test and Measurement Oxford University Press, 2nd Edition, 2011, ISBN 978-0-12-979621-2 (EN)

    Recommended reading

    Not applicable.

    Classification of course in study plans

    • Programme MPC-NCP Master's 2 year of study, winter semester, compulsory

    Type of course unit

     

    Lecture

    26 hod., optionally

    Teacher / Lecturer

    prof. Ing. Jaromír Hubálek, Ph.D.

    Syllabus

      • Introduction
      • Why do testing at all
        • General motivation
        • Yield
        • Cost of testing
        • Product quality and reliability
        • Ideal tests and real tests
        • Terms and Definitions
      • System on a chip development process
        • Milestones process steps, maturity phases
        • test in the product lifecycle
        • risk assessment - APP,FMEA
      • Design for Testability
        • Economics and Costs
        • Ad-hoc design techniques
        • Defects and fault models
        • Automatic Test Pattern Generation (ATPG,) Algorithm Example ( PODEM)
        • Scan Design
        • Boundary Scan
        • Built-in-self-test (BIST)
        • Memory Test
        • IDDQ test
        • Analog circuit DfT
      • Test Development
        • Test Development Flow – test specification
        • Automatic Test Equipment (ATE)
        • Digital test signal development
          • Test Vector Development
          • Timing and formatting in digital ATE
        • Analog test signal development
          • DSP based testing
            • Non coherent vs. Coherent measurements
            • Converter testing
            • Multi tone testing
        • Test Hardware Development
        • Test Program Development
        • Device Characterization
          • Statistical process control (SPC) – measurement capability
          • Guardbanding (Test Limit Management)
    • Production Test
      • IC Backend Production Flow
      • Testfloor infrastructure - ESD
      • Wafertest
      • Finaltest
      • Multi-site testing
      • Production Ramp Up
     

    Laboratory exercise

    26 hod., compulsory

    Teacher / Lecturer

    prof. Ing. Jaromír Hubálek, Ph.D.

    Syllabus

    1. Examples of testing chips on wafer using Keithley 4200A and 4-8 probes on Cascade M150. 

    2. Examples of LDO testing on a test board