Course detail
VHDL Seminar
FIT-IVHAcad. year: 2024/2025
Basic VHDL language constructs, lexical description, VHDL source code. Data types, data objects, data classes, data objects declaration. VHDL language commands. Advanced VHDL features, VHDL 93. Delay modelling, time scheduling in VHDL. Combinational circuits modelling, "don't cares", tri-state-output circuits. Sequential circuits modelling, Mealy and Moore automata. Models testing, test benches. Designing at algorithm, register-transfer, and gate levels. Modelling for synthesis. Semantics for simulation and synthesis, delay in model. Programming techniques, shared components, flattening and structuring. Case studies of complex digital circuits: UART, RISC processor, FIR filter.
Language of instruction
Number of ECTS credits
Mode of study
Guarantor
Department
Entry knowledge
Rules for evaluation and completion of the course
Aims
To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioural and structural description. This course is recommended as a co-requisite for INC and INP.
Study aids
Prerequisites and corequisites
Basic literature
Recommended reading
Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
Douša, J.: Jazyk VHDL, České vysoké učení technické v Praze. Elektrotechnická fakulta, Praha, 2003 (CS)
Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
Jasinski, R.: Effective Coding with VHDL: Principles and Best Practice. The MIT Press. 2016.
Pedroni, V. A.: Circuit Design and Simulation with VHDL (Second Edition). The MIT Press. 2011
Přednáškové materiály v elektronické podobě. (CS)
Elearning
Classification of course in study plans
Type of course unit
Seminar
Teacher / Lecturer
Syllabus
- Modern hardware design (design flow), hardware description languages (VHDL, Verilog), FPGA, introduction to digital systems.
- Basic VHDL language structure, lexical description, VHDL source code.
- Data types, data objects, object classes, data object declaration.
- VHDL language statements
- Advanced VHDL language properties, time delay and scheduling.
- Combination circuits description, three-state circuits.
- Synchronous sequential circuits description, finite state automata description, asynchronous sequential circuits.
- Circuits modeling and event based simulation, circuit testing, test design, functional simulation (ModelSIM), co-simulation.
- Circuit synthesis, constraints, synthesis for FPGA, time simulation.
- Advanced methods (pipelining, retiming, component sharing, flattening and structuring)
- Complex circuit case study: LED matrix display, UART, ETHERNET
- Complex circuit case study: RISC processor
- FPGA circuits, mass parallelism in cryptography (RC4, DES), DNA-alignment
Project
Teacher / Lecturer
Syllabus
Elearning