Course detail

Advanced Digital Systems

FIT-PCSAcad. year: 2013/2014

Combinatorial and sequential logic design techniques, algorithms, and tools review. Review of digital design target technologies (ASIC, FPGA). Algorithms for minimization of digital circuits. Advanced synthesis techniques (pipelining, retiming). Constraint conditions. High-level synthesis (scheduling, allocation, binding). High-level synthesis (loop synthesis). Digital design using CatapultC environment (basic statements in C/C++). Digital design using CatapultC environment (loops, memory access). Low power design methodologies.
Reconfigurable computing. Verification of digital circuits (OVM methodology).

Language of instruction

Czech

Number of ECTS credits

Mode of study

Not applicable.

Guarantor

doc. Dr. Ing. Otto Fučík

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

The students are able to design complex constrained digital systems using contemporary design techniques, high-level description language (C/C++) and professional CAD tools (CatapultC).

Prerequisites

Digital system design, basic programming skills.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

The course uses teaching methods in form of Lecture - 2 teaching hours per week, Computer exercise - 1 teaching hour per week, Projects - 1 teaching hour per week.

Assesment methods and criteria linked to learning outcomes

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Course curriculum

    Syllabus of lectures:
    • Combinatorial and sequential logic design techniques, algorithms, and tools review.
    • Review of digital design target technologies (ASIC, FPGA).
    • Algorithms for minimization of digital circuits.
    • Advanced synthesis techniques (pipelining, retiming).
    • Constraint conditions.
    • High-level synthesis (scheduling, allocation, binding).
    • High-level synthesis (loop synthesis).
    • Digital design using CatapultC environment (basic statements in C/C++).
    • Digital design using CatapultC environment (loops, memory access).
    • Low power design methodologies.
    • Reconfigurable computing.
    • Verification of digital circuits (OVM methodology).

    Syllabus of computer exercises:
    • Synthesis of the basic logic circuits, pipelining, retiming.
    • Constraint conditions.
    • Basic techniques for digital design using CatapultC environment.
    • Advanced techniques for digital design using CatapultC environment.
    • Verification of digital circuits.

    Syllabus - others, projects and individual work of students:
    • Individual project focused on digital design using CatapultC environment.

Work placements

Not applicable.

Aims

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.

Specification of controlled education, way of implementation and compensation for absences

Written mid-term exam and project in due dates.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008 (EN)

Recommended reading

Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011 (EN)
Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996 (EN)

Classification of course in study plans

  • Programme IT-MSC-2 Master's

    branch MBS , 0 year of study, winter semester, elective
    branch MIN , 0 year of study, winter semester, elective
    branch MIS , 0 year of study, winter semester, elective
    branch MMI , 0 year of study, winter semester, compulsory-optional
    branch MMM , 0 year of study, winter semester, elective
    branch MPV , 2 year of study, winter semester, compulsory
    branch MBI , 0 year of study, winter semester, compulsory-optional
    branch MGM , 0 year of study, winter semester, compulsory-optional
    branch MSK , 0 year of study, winter semester, elective

Type of course unit

 

Lecture

26 hod., optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík

Syllabus

  • Combinational and sequential logic design techniques, algorithms, and tools review.
  • Structured design concept. Design strategies. Design decomposition. Design tools.
  • Introduction to VHDL
  • Basic features of VHDL. Simulation and synthesis.
  • Basic VHDL modeling techniques.
  • Algorithmic level design.
  • Register Level Design.
  • HDL-based design techniques. Constrained design.
  • ASIC and PLD design process. Fast prototyping.
  • Modeling for synthesis.
  • Top-down design methodology in VHDL.
  • Design case study.
  • Design automation algorithms. HW/SW co-design.

Exercise in computer lab

10 hod., optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík

Syllabus

  • Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
  • Combinational logic circuits modeling and simulation using VHDL.
  • Sequential logic circuits modeling and simulation using VHDL.
  • A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.

Project

16 hod., optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík