Course detail
Programmable Logic Devices
FEKT-LPLDAcad. year: 2011/2012
The course is aimed to extend the knowledge of digital technique. Types of programmable devices: SPLD, CPLD and FPGA devices. Special function blocks used in PLD devices. Text description (HDL languages) and graphical description of PLD subsystems. CAD development systems and their use for simulation of digital subsystems (combinational circuits, counters, state machines), synthesis and implementation into CPLD and FPGA devices. Functional verification of designed subsystems by programming laboratory kits.
Language of instruction
Number of ECTS credits
Mode of study
Guarantor
Department
Learning outcomes of the course unit
Prerequisites
Co-requisites
Planned learning activities and teaching methods
Assesment methods and criteria linked to learning outcomes
Course curriculum
Architecture of FPGAs, FPGA on the market, future of FPGAs.
Using microcontrollers and other advanced features of FPGAs (gigabit transceivers, MAC, PCI-Express), system on chip (SoC).
VHDL basics, typical coding examples, IP cores and its usage.
Verification: testbench, behavioral simulation, post PAR simulation.
Design of PLD-based systems: power, signal integrity, packing, PCB.
Work placements
Aims
Specification of controlled education, way of implementation and compensation for absences
Recommended optional programme components
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Basic literature
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Classification of course in study plans
Type of course unit
Lecture
Teacher / Lecturer
Syllabus
Simple PLDs, their functional blocks, macrocells of GAL 16V8 and 20V8 devices. Other SPLD types, their labeling and parameters.
Special PLD types (ZeroPower, low voltage types and others). Programming, programmers
Complex PLD and FPGA devices - structure, basic properties
Implementation of complex combinational functions - multiple-pass and iterative structures, adder, comparator
Asynchronous latches RS and D in PLD structure
Synchronous systems in PLDs: Use of T-type flipflops and EX-OR gates. Mutual conversion of different flipflop types, emulation
One- and bidirectional binary counters, counters with shortened cycle - their description in HDL, number of terms
BCD counters, their implementation in PLD devices
Gray code counters with full and shortened cycle
LFSR counters - structure, advantages and disadvantages, their use
Return of counters into working cycle
State machines (SM): Moore and Mealy type, HDL description, their compilation to SOP form
Simplifying of SM - equivalent states, their finding. State coding for PLDs and FPGAs. Algorithmic description of SM
Timing in programmable devices, pipelining
FPGA devices - additional blocks: I/O standards, memory elements, blocks for frequency synthesis and for further handling of clock signals
Implementation of processors, use of intellectual property blocks
Boundary scan, metastability
Exercise in computer lab
Teacher / Lecturer
Syllabus
ABEL language: description of combinational systems - SOP form, compilation, simulation, more complex statements like WHEN-THEN-ELSE, their compilation. Example: priority encoder
Synchronous systems: description methods, examples of various counter types
Fundamentals of VHDL language, behavioral and structural description, concurrent statements and processes. Hierarchically composed designs
Combinational logic description in VHDL, synthesis. Unwanted latch and how to avoid it
Behavioral description of edge-triggered registers. Binary, decade, LFSR counters
State machines: graphical and textual form of state diagram, example: bit sequence detectors. Graphical editors of state diagrams, StateCAD tool
Simulation, synthesis and implementation of the designs (continuously in all exercises)