Course detail
Microprocessors
FEKT-BMICAcad. year: 2011/2012
Representation of numbers in computer. Logical functions, Bool's algebraic, combination and sequence circuits. Principles of microprocessor. Addressing. Subrutins, interrups, stack utilisation. Von Neuman and harward conception of computer. Overlapping and pipelining. Superscalar architecture. CISC a RISC processors. Multiprocessor systems and processors fields. Microcontrollers Freescale HCS12: SW model. Instruction set. Peripherals: Parallel Input/Output, A/D convertor, timer system, SCI, SPI, IIC, PWM. Segmentation, paging, memory virtualisations, logical and fyzical address, MMU. Microprocessors Intel with IA32/IA32e architecture: addressing modes, virtual addressing, user and supervisor mode, real mode and protected mode, memory protection, proces switching. Paging unit. Interrupts. Embedded systems.
Language of instruction
Czech
Number of ECTS credits
6
Mode of study
Not applicable.
Guarantor
Learning outcomes of the course unit
Students are able to design combination and sequence logical circuitry, microprocessor circuitry and create SW equipement for microprocessor systems.
Prerequisites
Base knowledge of C language programming.
Co-requisites
Not applicable.
Planned learning activities and teaching methods
Teaching methods depend on the type of course unit as specified in the article 7 of BUT Rules for Studies and Examinations.
Assesment methods and criteria linked to learning outcomes
Work of students is evaluated during study by tests in exercises. They can obtain maximum 40 points by these tests during semester.
Final examination is evaluated by 60 points at maximum.
Final examination is evaluated by 60 points at maximum.
Course curriculum
1. Introduction. Definition of logical circuit, two states signals. Mathematical logic, logical function, Boole's algebraic. Completely and uncompletely defined logical function. Description of logic function by table and by algebraic form (UDNF, UKNF). Simplification of logical functions. Algebraic simplification. Realization of logical circuits wits NAND and NOR. Karnaug's map.
2. Base combination logical blocks (binary decoder, multiplexor, demultiplexor, priority coder, digital comparator, code transformation).
3. Principal of flip-flop, RS, D, JK, T, master-slave flip-flop. Sequence logical circuits: finite state automat, Huffman's model of automat, Mealy automat, Moor automat.
4. Data registers, shift registers, synchronous and asynchronous counters, deviders.
5. Von Neumanns` conception of computer. Base cycle of computer. Computer block diagram, ALU, controller, registers, memory, peripheral devices. Memory organization. Microprocessor, microcontroller, digital signal processor, digital signal controller.
6. Program, instruction, instruction set, types of instruction, number of operands, instruction set architecture. Addressing modes.
7. Machine code, assembler. Subrutins , stacks manipulation. Difference between subrutin and macro. Stack and C language.
8. Programmed I/O: polling, interrupt-driven I/O, using DMA. Synchronous and asynchronous interrupts. Interrupt servicing. Mask, nonmask and pseudomask interrupts. Reset.
9. Microcontrollers Motorola HCS12 family: ports, CRG units (oscillator, PLL, real-time interrupt , Watchdog (COP)), timers, A/D convertor..
10. Von Neumann, Harvard and modified Harvard architectures. Pipelining, problems of pipelining.. Superscalar architecture. Multiprocessor systems and processor fields.
11. Memories, memory parameter. Principle and property of memory: SRAM, DRAM, SDRAM, DDR RAM, FeRAM, MRAM, EPROM, EEPROM, FLASH.
12.Memory bus interface. Principle of locality, memory hierarchy, memory cache.
13. Memory management. No memory abstraction. Dynamic relocation, base and limit registers. MMU. Paging and segmentation. Virtual memory.
2. Base combination logical blocks (binary decoder, multiplexor, demultiplexor, priority coder, digital comparator, code transformation).
3. Principal of flip-flop, RS, D, JK, T, master-slave flip-flop. Sequence logical circuits: finite state automat, Huffman's model of automat, Mealy automat, Moor automat.
4. Data registers, shift registers, synchronous and asynchronous counters, deviders.
5. Von Neumanns` conception of computer. Base cycle of computer. Computer block diagram, ALU, controller, registers, memory, peripheral devices. Memory organization. Microprocessor, microcontroller, digital signal processor, digital signal controller.
6. Program, instruction, instruction set, types of instruction, number of operands, instruction set architecture. Addressing modes.
7. Machine code, assembler. Subrutins , stacks manipulation. Difference between subrutin and macro. Stack and C language.
8. Programmed I/O: polling, interrupt-driven I/O, using DMA. Synchronous and asynchronous interrupts. Interrupt servicing. Mask, nonmask and pseudomask interrupts. Reset.
9. Microcontrollers Motorola HCS12 family: ports, CRG units (oscillator, PLL, real-time interrupt , Watchdog (COP)), timers, A/D convertor..
10. Von Neumann, Harvard and modified Harvard architectures. Pipelining, problems of pipelining.. Superscalar architecture. Multiprocessor systems and processor fields.
11. Memories, memory parameter. Principle and property of memory: SRAM, DRAM, SDRAM, DDR RAM, FeRAM, MRAM, EPROM, EEPROM, FLASH.
12.Memory bus interface. Principle of locality, memory hierarchy, memory cache.
13. Memory management. No memory abstraction. Dynamic relocation, base and limit registers. MMU. Paging and segmentation. Virtual memory.
Work placements
Not applicable.
Aims
To familiar student with design of combination and sequence logical circuits, to give students base informations about principles and design of microprocessors systems, software design for systems with microprocessors and microcontrollers and embedded systems.
Specification of controlled education, way of implementation and compensation for absences
The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.
Recommended optional programme components
Not applicable.
Prerequisites and corequisites
- compulsory prerequisite
Computers and Programming 1
Basic literature
Ličev L., Morkes D., Procesory - architektura, funkce, použití. Brno: Computer press, 1999. 260 s. ISBN 80-7226-172-X. (CS)
Pinker J., Poupa M. Císlicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
Pinker J., Poupa M. Císlicové systémy a jazyk VHDL. Praha: BEN, 2006. 349 s. ISBN 80-7300-198-5. (CS)
Recommended reading
Not applicable.
Classification of course in study plans
Type of course unit
Lecture
26 hod., optionally
Teacher / Lecturer
Syllabus
1. Mathematical logic, logical function, Boole's algebraic. Table, map and algebraical form of logical function. Simplification of logical functions.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
2. Combination logical circuits (switches, decoders, multiplectors, demultiplectors). Sequencal logical circuits: flip-flop.
3. Sequencal logical circuits: Huffman's model of automat, Mealy automat, Moor automat. Registers, counters, deviders, shift registers.
4. Memories. Computer block diagram, CPU - ALU, controller, registers. Microprocessor, microcomputer, microcontroller, DSP. Base principle microprocessor working. Clock cycle, phase, machine cycle, instruction cycle.
4. Addressing. Subrutins, interrupts, stacks utilisation. Von Neumann, Harvard modified Harvard microprocessor architectures. Overlapping. Pipelining.
5. Microcontrollers Motorola HCS12 family: Programmer model, ALU. Addressing modes. Operational modes and memory maps.
6. HCS12: Operating modes. Ports, MEBI units, Key Wake up function, PIM units. CRG units (oscilators, PLL, real-time interrup (RTI), Watchdog (COP)).
7. HCS12: A/D convertor. Timer subsystem: Imput capture function. Output compare function. Pulse accumulatos.
8.HCS12: Serial Comunication Interface (SCI). Serial Peripheral Interface (SPI). Low power modes WAIT and STOP.
9. HCS12: Connectios microprocessor with external components as memoris, A/D and D/A convertors, keyboard, display.
10. Segmentation, paging and virtual memory. Intel IA32 (I386) architecture: Programmer model. Addressing modes. Memory addressing and I/O addressing.
11. IA32: Privilegy levels. Local and global address space. GDI and LDI tables. Logical address, linear address. Segment descriptors. Data segment Acces.
12. IA32: Calling instruction segment. Gates. Task switching. Interrupts in real and protected mode. Paging unit.
13. Architecture of Intel pentium P6. MMX, SSE, SSE2, SSE3 instructions. New states of art in Intel microprocessors. Embedded systems.
Exercise in computer lab
39 hod., compulsory
Teacher / Lecturer
Syllabus
1. Decimal, hexadecimal and binary numbers. Addition, substraction binary numbers. First complemment. Miltiplication and division binary numbers.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.
2. Floating point numbers by IEEE-754 standard. Logical function simplification, binary sumation circuit design.
3. Sequece logical circuit design.
4. Assembly language prougram - addition and substraction 16 bit and 32 bit numbers.
5. Assembly language program - moving field of numbers. Assembly language program for sorting field of numbers.
6. Assembly language program - multiplication two 16 bit numbers with using shift instructions.
Assembler programme for multiplication two 16 bit numbers with using MUL instructions.
7. Assembly language program - stack utilisation.
8. C language program - utilisation of binary HCS12 I/O ports.
9. C programme - utilisation of HCS12 Real Time Interrupt.
10. C programme - utilisation of HCS12 serial comunication interface.
11. C programme - utilisation of HCS12 A/D convertor.
12.C programme - utilisation of HCS12 Output Compare and Imput Capture functions.
13. Final test.