Course detail

The Principles of Testable Design Synthesis

FIT-PTDAcad. year: 2010/2011

Not applicable.

Language of instruction

Czech, English

Mode of study

Not applicable.

Guarantor

doc. Ing. Zdeněk Kotásek, CSc.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Not applicable.

Prerequisites

Not applicable.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Not applicable.

Course curriculum

Not applicable.

Work placements

Not applicable.

Aims

Not applicable.

Specification of controlled education, way of implementation and compensation for absences

Not applicable.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

M. Abramovici, M. A. Breuer, D. Friedman: Digital Systems Testing and Testable Design: Revised Printing, Computer Society Press, 1995, ISBN 0-7803-1062-4, 680 stran A. L. Crouch: Design-for-Test for Digital IC's and Embedded Core Systems, Prentice Hall, 1999, ISBN 0-13-084827-1, 347 stran P. Michel, U. Lauther, P. Duzzy: The Synthesis Approach to Digital System Design, The Kluwer International Series in Engineering and Computer Science, ISBN 0-7923-9199-3, 375 stran

Recommended reading

Not applicable.

Classification of course in study plans

  • Programme CSE-PHD-4 Doctoral

    branch DVI4 , 0 year of study, winter semester, elective

  • Programme CSE-PHD-4 Doctoral

    branch DVI4 , 0 year of study, winter semester, elective

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

doc. Ing. Zdeněk Kotásek, CSc.

Syllabus

  • The Principles of Digital System Synthesis, the Implementation of Testability Principles during the Synthesis.
  • The Testability of a Digital Circuit, Controlability and Observability Concepts, Testability Measures.
  • The Evolution of Digital Circuit Testing Methods – the Principles of Increasing Controlability/Observability Parameters of Internal Nodes.
  • Test Points Techniques. The Implementation of Scan Registers to Increase Controlability/Observability
  • Full Scan Methods: Serial Methods (LSSD, Scan Path, Scan Set), Parallel Methods (RAS, ARAS).
  • Partial Scan Methods. The Utilisation of Full and Partial Scan Methods in Synthesis.
  • PLA Testing, Testable PLA Synthesis.
  • Built-in Self Test.
  • Test Pattern Generator, Test Response Analyser.
  • BIST Architectures, Hierarchical Structure of BIST Architectures.
  • CSTP, BILBO.
  • Self-checking design.
  • Boundary Scan. Test of Connections.