Reducing memory in high-speed packet classification

Reducing memory in high-speed packet classification

Paper in proceedings outside WoS and Scopus

Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.

Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.

FPGA, SRAM, hardware, parallelism, classification

FPGA, SRAM, hardware, parallelism, classification

PUŠ, V.; KOŘENEK, J.

2013

09.10.2012

Frederick University

Limassol

978-1-4577-1377-4

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference

437

442

6

https://www.fit.vut.cz/research/publication/10167/

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