Publication detail

Reducing memory in high-speed packet classification

PUŠ, V. KOŘENEK, J.

Original Title

Reducing memory in high-speed packet classification

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.

Keywords

FPGA, SRAM, hardware, parallelism, classification

Authors

PUŠ, V.; KOŘENEK, J.

RIV year

2012

Released

9. 10. 2012

Publisher

Frederick University

Location

Limassol

ISBN

978-1-4577-1377-4

Book

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference

Pages from

437

Pages to

442

Pages count

6

URL

https://www.fit.vut.cz/research/publication/10167/

BibTex

@inproceedings{BUT97051,
  author="Viktor {Puš} and Jan {Kořenek}",
  title="Reducing memory in high-speed packet classification",
  booktitle="Proceedings of the 8th International Wireless Communications and Mobile Computing Conference",
  year="2012",
  pages="437--442",
  publisher="Frederick University",
  address="Limassol",
  isbn="978-1-4577-1377-4",
  url="https://www.fit.vut.cz/research/publication/10167/"
}