Publication result detail

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

ZACHARIÁŠOVÁ, M.

Original Title

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

English Title

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.

English abstract

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.

Keywords

functional verification, hardware acceleration, genetic algorithm, optimization

Key words in English

functional verification, hardware acceleration, genetic algorithm, optimization

Authors

ZACHARIÁŠOVÁ, M.

RIV year

2013

Released

12.09.2012

Publisher

Czech Technical University

Location

Praha

ISBN

978-80-01-05106-1

Book

Počítačové architektury a diagnostika

Pages from

73

Pages to

78

Pages count

6

BibTex

@inproceedings{BUT97039,
  author="Marcela {Zachariášová}",
  title="Acceleration of Functional Verification in the Development Cycle of Hardware Systems",
  booktitle="Počítačové architektury a diagnostika",
  year="2012",
  pages="73--78",
  publisher="Czech Technical University",
  address="Praha",
  isbn="978-80-01-05106-1"
}