Kompresor a dekompresor hlaviček pro 1 Gbps Ethernet, implementace pro FPGA

1 Gbps Ethernet header compressor and decompressor, FPGA implementation

Software

Kompresor a dekompresor hlaviček pro 1 Gbps Ethernet slouží k hardwarové implementaci komprese TCP/IP a UDP/IP hlaviček Ethernetového toku. Navržená komprese pracuje na úrovni linkové vrstvy. Modul kompresoru a dekompresoru je realizován tak, aby docházelo k co nejmenší latenci přenášených dat. Implementace byla testována na FPGA obvodu Altera Cyclone III (EP3C40F484C7).

The header compressor and decompressor is designed for the hardware compression of 1 Gbps Ethernet headers like TCP/IP and UDP/IP. An implemented compression and decompression modules were designed with respect to the minimal delay of processed data, they work at link layer. The implementation was realized and tested at FPGA device Altera Cyclone III (EP3C40F484C7).

FPGA, compression, header, dictionary

FPGA, compression, header, dictionary

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only the provider uses the result

Use of the result by another entity is possible without acquiring a license (the result is not licensed)

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