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KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z.
Original Title
Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration
English Title
Type
Paper in proceedings outside WoS and Scopus
Original Abstract
In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.
English abstract
Keywords
FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller
Key words in English
Authors
Released
28.02.2012
Publisher
Politecnico di Milano
Location
Annecy
Book
The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)
Pages from
1
Pages to
4
Pages count
BibTex
@inproceedings{BUT91473, author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}", title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration", booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)", year="2012", pages="1--4", publisher="Politecnico di Milano", address="Annecy" }