Publication result detail

Evolutionary Optimization of Complex Digital Circuits

VAŠÍČEK, Z.; SEKANINA, L.

Original Title

Evolutionary Optimization of Complex Digital Circuits

English Title

Evolutionary Optimization of Complex Digital Circuits

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

This contribution is based on the paper Formal Verification of Candidate Solutions for Post-Synthesis Evolutionary Optimization in Evolvable Hardware that has been published in Genetic Programming and Evolvable Machines journal, Volume 12, Number 3, p. 305-327.

English abstract

This contribution is based on the paper Formal Verification of Candidate Solutions for Post-Synthesis Evolutionary Optimization in Evolvable Hardware that has been published in Genetic Programming and Evolvable Machines journal, Volume 12, Number 3, p. 305-327.

Keywords

circuit synthesis, circuit optimization, evolutionary design, satisfiability, formal verification, combinational equivalence checking

Key words in English

circuit synthesis, circuit optimization, evolutionary design, satisfiability, formal verification, combinational equivalence checking

Authors

VAŠÍČEK, Z.; SEKANINA, L.

Released

13.10.2011

Publisher

Masaryk University

Location

Brno

ISBN

978-80-214-4305-1

Book

7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

127

Pages to

127

Pages count

1

BibTex

@inproceedings{BUT91278,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Evolutionary Optimization of Complex Digital Circuits",
  booktitle="7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2011",
  pages="127--127",
  publisher="Masaryk University",
  address="Brno",
  isbn="978-80-214-4305-1"
}