Hardware Architecture for Packet Classification with Prefix Coloring

Hardware Architecture for Packet Classification with Prefix Coloring

Paper in proceedings outside WoS and Scopus

Packet classification is a widely used operation in network security
devices. As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in hardware can achieve multigigabit
speeds, but suffer with great memory overhead. We propose a new algorithm
and hardware architecture which reduces memory requirements of
decomposition based methods for packet classification. The algorithm uses
prefix coloring to reduce large amount of Cartesian product rules at the
cost of an additional pipelined processing and a few bits added into
results of the longest prefix match operation. The proposed hardware
architecture is designed as a processing pipeline with the throughput of
266 million packets per second using commodity FPGA and one external
memory. The greatest strength of the algorithm is the constant time
complexity of the search operation, which makes the solution resistant to
various classes of network security attacks.

Packet classification is a widely used operation in network security
devices. As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in hardware can achieve multigigabit
speeds, but suffer with great memory overhead. We propose a new algorithm
and hardware architecture which reduces memory requirements of
decomposition based methods for packet classification. The algorithm uses
prefix coloring to reduce large amount of Cartesian product rules at the
cost of an additional pipelined processing and a few bits added into
results of the longest prefix match operation. The proposed hardware
architecture is designed as a processing pipeline with the throughput of
266 million packets per second using commodity FPGA and one external
memory. The greatest strength of the algorithm is the constant time
complexity of the search operation, which makes the solution resistant to
various classes of network security attacks.

FPGA, SRAM, hardware, parallelism, classification

FPGA, SRAM, hardware, parallelism, classification

PUŠ, V.; KAJAN, M.; KOŘENEK, J.

2012

13.04.2011

IEEE Computer Society

Cottbus

978-1-4244-9753-9

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

231

236

6

https://www.fit.vut.cz/research/publication/9564/

paper