Publication result detail

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A.

Original Title

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

English Title

Design and Simulation of High Performance Parallel Architectures Using the ISAC Language

Type

Peer-reviewed article not indexed in WoS or Scopus

Original Abstract

Most of modern embedded systems for multimedia and network applications are based on parallel data stream processing. The data processing can be done using very long instruction word processors (VLIW), or using more than one high performance application-specific instruction set processor (ASIPs), or even by their combination on single chip.

Design and testing of these complex systems is time-consuming and iterative process. Architecture description languages (ADLs) are one of the most effective solutions for single processor design. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in nowadays ADLs. This article presents utilization of new extensions for existing architecture description language ISAC. These extensions are used for easy and fast prototyping and testing of parallel based systems and processors.

This article extends the previous publication on RTES 2010 conference.

English abstract

Most of modern embedded systems for multimedia and network applications are based on parallel data stream processing. The data processing can be done using very long instruction word processors (VLIW), or using more than one high performance application-specific instruction set processor (ASIPs), or even by their combination on single chip.

Design and testing of these complex systems is time-consuming and iterative process. Architecture description languages (ADLs) are one of the most effective solutions for single processor design. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in nowadays ADLs. This article presents utilization of new extensions for existing architecture description language ISAC. These extensions are used for easy and fast prototyping and testing of parallel based systems and processors.

This article extends the previous publication on RTES 2010 conference.

Keywords

Architecture description language, ISAC, VLIW, multiprocessor system on a chip, simulation, debugging

Key words in English

Architecture description language, ISAC, VLIW, multiprocessor system on a chip, simulation, debugging

Authors

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D.; MASAŘÍK, K.; HUSÁR, A.

RIV year

2012

Released

01.02.2011

Publisher

Global Science & Technology Forum

Location

Singapur

Book

GSTF International Journal on Computing

ISBN

2010-2283

Periodical

GSTF International Journal on Computing

Volume

1

Number

2

State

Republic of Singapore

Pages from

97

Pages to

106

Pages count

10

URL

http://dl4.globalstf.org/?wpsc-product=design-and-simulation-of-high-performance-parallel-architectures-using-the-isac-language

BibTex

@article{BUT76296,
  author="Zdeněk {Přikryl} and Jakub {Křoustek} and Tomáš {Hruška} and Dušan {Kolář} and Karel {Masařík} and Adam {Husár}",
  title="Design and Simulation of High Performance Parallel Architectures Using the ISAC Language",
  journal="GSTF International Journal on Computing",
  year="2011",
  volume="1",
  number="2",
  pages="97--106",
  doi="10.5176/2010-2283\{_}1.2.46",
  issn="2010-2283",
  url="http://dl4.globalstf.org/?wpsc-product=design-and-simulation-of-high-performance-parallel-architectures-using-the-isac-language"
}