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Detail aplikovaného výsledku
ŠKARVADA, J.; KOTÁSEK, Z.
Original Title
Set of tools for RTL circuits testability analysis
English Title
Type
Software
Abstract
Homepage of the product: http://www.fit.vutbr.cz/~skarvada/ruz/Developed tools can be used for automatic transformation of digital circuit design written in structural VHDL to formal model that was developed on DCS. It is possible to use them for transparent data paths (I-paths) search, testability analysis, scan chain design. Custom cell libraries can be used.
Abstrakt aglicky
Keywords
RTL, testability analysis, I-paths search, formal model, scan chain design
Key words in English
Location
Domácí stránka produktu: http://www.fit.vutbr.cz/~skarvada/ruz/
Licence fee
In order to use the result by another entity, it is always necessary to acquire a license
www
https://www.fit.vut.cz/research/product/56/