Publication result detail

Imaging Algorithm Speedup Using Co-Design

ZEMČÍK, P.; FUČÍK, O.; RICHTER, M.; VALENTA, P.

Original Title

Imaging Algorithm Speedup Using Co-Design

English Title

Imaging Algorithm Speedup Using Co-Design

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.

English abstract

The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.

Keywords

co-design, image processing, FPGA

Key words in English

co-design, image processing, FPGA

Authors

ZEMČÍK, P.; FUČÍK, O.; RICHTER, M.; VALENTA, P.

RIV year

2011

Released

11.06.2001

Publisher

Faculty of Electrical Engineering and Informatics, University of Technology Košice

Location

Štrbské Pleso

ISBN

80-227-1542-5

Book

Summaries Volume Process Control 01

Pages from

96

Pages to

97

Pages count

2

BibTex

@inproceedings{BUT5744,
  author="Pavel {Zemčík} and Otto {Fučík} and Miloslav {Richter} and Pavel {Valenta}",
  title="Imaging Algorithm Speedup Using Co-Design",
  booktitle="Summaries Volume Process Control 01",
  year="2001",
  pages="96--97",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Štrbské Pleso",
  isbn="80-227-1542-5"
}