Publication detail

Verification of Digital Design Using Non-Synthesizable Description

KOLOUCH, J.

Original Title

Verification of Digital Design Using Non-Synthesizable Description

Type

conference paper

Language

English

Original Abstract

A verification method suitable for lower-style HDL model development is presented. It allows the use of the try-and-correct method that can be advantageous in writing models intended for synthesis. It can be used in laboratory exercises with WebPACK software that is freely available on www pages of Xilinx.

Keywords

HDL language, verification, simulation, FPGA

Authors

KOLOUCH, J.

RIV year

2002

Released

15. 5. 2002

Publisher

Slovak University of Technology in Bratislava

Location

Bratislava

ISBN

80-227-1700-2

Book

Radioelektronika 2002, Conference Proceedings

Pages from

417

Pages to

420

Pages count

4

BibTex

@inproceedings{BUT5248,
  author="Jaromír {Kolouch}",
  title="Verification of Digital Design Using Non-Synthesizable Description",
  booktitle="Radioelektronika 2002, Conference Proceedings",
  year="2002",
  pages="417--420",
  publisher="Slovak University of Technology in Bratislava",
  address="Bratislava",
  isbn="80-227-1700-2"
}