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KLEDROWETZ, V.; HÁZE, J.
Original Title
Basic Block of Pipelined ADC Design Requirements
English Title
Type
Peer-reviewed article not indexed in WoS or Scopus
Original Abstract
The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to-Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.
English abstract
Keywords
Pipelined ADC, MDAC, SC technique, MATLAB model, thermal noise, opamp.
Key words in English
Authors
RIV year
2012
Released
11.04.2011
Publisher
VUT v Brně
Location
Brno
ISBN
1210-2512
Periodical
Radioengineering
Volume
2011
Number
1
State
Czech Republic
Pages from
234
Pages to
238
Pages count
5
BibTex
@article{BUT50694, author="Vilém {Kledrowetz} and Jiří {Háze}", title="Basic Block of Pipelined ADC Design Requirements", journal="Radioengineering", year="2011", volume="2011", number="1", pages="234--238", issn="1210-2512" }