Publication result detail

Design of Arbiters and Allocators Based on Multi-Terminal BDDs

DVOŘÁK, V.; MIKUŠEK, P.

Original Title

Design of Arbiters and Allocators Based on Multi-Terminal BDDs

English Title

Design of Arbiters and Allocators Based on Multi-Terminal BDDs

Type

Peer-reviewed article not indexed in WoS or Scopus

Original Abstract

Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.

English abstract

Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.

Keywords

Multi-Terminal BDDs, LUT cascades, iterative disjunctive decomposition, arbiter circuits, allocators.

Key words in English

Multi-Terminal BDDs, LUT cascades, iterative disjunctive decomposition, arbiter circuits, allocators.

Authors

DVOŘÁK, V.; MIKUŠEK, P.

RIV year

2012

Released

28.07.2010

ISBN

0948-6968

Periodical

JOURNAL OF UNIVERSAL COMPUTER SCIENCE

Volume

16

Number

14

State

Republic of Austria

Pages from

1826

Pages to

1852

Pages count

27

URL

https://www.fit.vut.cz/research/publication/9348/

BibTex

@article{BUT50516,
  author="Václav {Dvořák} and Petr {Mikušek}",
  title="Design of Arbiters and Allocators Based on Multi-Terminal BDDs",
  journal="JOURNAL OF UNIVERSAL COMPUTER SCIENCE",
  year="2010",
  volume="16",
  number="14",
  pages="1826--1852",
  issn="0948-695X",
  url="https://www.fit.vut.cz/research/publication/9348/"
}

Documents

Dvorak-Arbiters