Power Conscious RTL Test Scheduling

Power Conscious RTL Test Scheduling

Paper in proceedings outside WoS and Scopus

In the paper, a methodology of power conscious RTL test
scheduling is described. The methodology is based on the
fact that circuit under analysis (CUA) is partitioned into
testable blocks (TB), the information about the partitioning
is the input information for the methodology. TBs are
mapped into AMI platform, for each TB the sequences of
test vectors are then derived, a professional tool is used
for this purpose. The sequences of test vectors are then reordered
with the goal to reduce power consumption during
test application by reducing switching activities. The power
consumption estimation is combined with the implemented
platform which allows to gain more precise results. The
values of TBs power consumption are then used in RTL test
scheduling methodology. The goal is to find test schedule
with lowest test application time and lower power consumption
than the required maximal value.

In the paper, a methodology of power conscious RTL test
scheduling is described. The methodology is based on the
fact that circuit under analysis (CUA) is partitioned into
testable blocks (TB), the information about the partitioning
is the input information for the methodology. TBs are
mapped into AMI platform, for each TB the sequences of
test vectors are then derived, a professional tool is used
for this purpose. The sequences of test vectors are then reordered
with the goal to reduce power consumption during
test application by reducing switching activities. The power
consumption estimation is combined with the implemented
platform which allows to gain more precise results. The
values of TBs power consumption are then used in RTL test
scheduling methodology. The goal is to find test schedule
with lowest test application time and lower power consumption
than the required maximal value.

Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming

Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

2010

02.06.2008

IEEE Computer Society

Los Alamitos

978-0-7695-3277-6

Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools

721

728

8

https://www.fit.vut.cz/research/publication/8700/

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