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KOŘENEK, J.; KOBIERSKÝ, P.
Original Title
Intrusion Detection System Intended for Multigigabit Networks
English Title
Type
Paper in proceedings outside WoS and Scopus
Original Abstract
Network intrusion detection systems (IDS) are becoming an important toolfor securing critical information and infrastructure. Currentsoftware-based IDS often fails to keep up with high-speed network links soa hardware based IDS is requested. This paper deals with design andimplementation of complete hardware accelerated IDS solution based onField-Programmable Gate Array (FPGA). Core generator for automatic mappingof IDS rules to FPGA logic was designed to assure fast packetclassification and high speed pattern matching. Proposed architecture hasbeen evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6Xcard theoretical throughput 6.4~Gbps was achieved for all Snort rules. Thedesigned system can be configured by rules described in Snort format usingweb interface.
English abstract
Keywords
Traffic Scanner, Snort, IDS, pattern matching
Key words in English
Authors
Released
24.08.2007
Publisher
IEEE Computer Society
Location
Krakow
ISBN
978-1-4244-1161-0
Book
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
Pages from
361
Pages to
364
Pages count
4
BibTex
@inproceedings{BUT28816, author="Jan {Kořenek} and Petr {Kobierský}", title="Intrusion Detection System Intended for Multigigabit Networks", booktitle="2007 IEEE Design and Diagnostics of Electronic Circuits and Systems", year="2007", pages="361--364", publisher="IEEE Computer Society", address="Krakow", isbn="978-1-4244-1161-0" }