Publication result detail

Design of Integer Phase Locked Loop

HÁZE, J.; VRBA, R.; FUJCIK, L.; PROKOP, R.

Original Title

Design of Integer Phase Locked Loop

English Title

Design of Integer Phase Locked Loop

Type

Paper in proceedings (conference paper)

Original Abstract

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

English abstract

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Keywords

phase locked-loop

Key words in English

phase locked-loop

Authors

HÁZE, J.; VRBA, R.; FUJCIK, L.; PROKOP, R.

Released

16.12.2007

Publisher

Novotný

Location

Brno

ISBN

978-80-214-3534-6

Book

MIKROSYN. Nové trendy v mikroelektronických systémech a nanotechnologiích.. Seminář o výsledcích výzkumného záměru MSM 0021630503 v roce 2007. Sborník příspěvků

Pages from

27

Pages to

34

Pages count

7

BibTex

@inproceedings{BUT28635,
  author="Jiří {Háze} and Radimír {Vrba} and Lukáš {Fujcik} and Roman {Prokop}",
  title="Design of Integer Phase Locked Loop",
  booktitle="MIKROSYN. Nové trendy v mikroelektronických systémech a nanotechnologiích.. Seminář o výsledcích výzkumného záměru MSM 0021630503 v roce 2007. Sborník příspěvků",
  year="2007",
  pages="27--34",
  publisher="Novotný",
  address="Brno",
  isbn="978-80-214-3534-6"
}