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STRAKA, M.; KOTÁSEK, Z.; WINTER, J.
Original Title
Digital Systems Architectures Based on On-line Checkers
English Title
Type
Paper in proceedings outside WoS and Scopus
Original Abstract
In this paper, we present a methodology for generatingVHDL descriptions of hardware checkers is presented. It isshown how the methodology can be used to generate on-linecheckers of communication protocols, counters, decoders,registers, comparators, etc. It is also demonstrated how achecker for more complex structures can be developed. Wedescribe the possibilities of utilizing this approach in the designof Fault Tolerant Systems (FTS). Experimental resultsin terms of FPGA resources needed to synthesize differenttypes of checkers are presented.
English abstract
Keywords
Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols
Key words in English
Authors
RIV year
2010
Released
13.05.2008
Publisher
IEEE Computer Society
Location
Parma
ISBN
978-0-7695-3277-6
Book
11th EUROMICRO Conference on Digital System Design DSD 2008
Pages from
81
Pages to
87
Pages count
8
URL
https://www.fit.vut.cz/research/publication/8621/
Full text in the Digital Library
http://hdl.handle.net/
BibTex
@inproceedings{BUT27769, author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}", title="Digital Systems Architectures Based on On-line Checkers", booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008", year="2008", pages="81--87", publisher="IEEE Computer Society", address="Parma", isbn="978-0-7695-3277-6", url="https://www.fit.vut.cz/research/publication/8621/" }
Documents
dsd08