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VAŠÍČEK, Z.; SEKANINA, L.
Original Title
Novel Hardware Implementation of Adaptive Median Filters
English Title
Type
Paper in proceedings (conference paper)
Original Abstract
A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%. In addition to filtering, adaptive median filters can be also used as detectors of corrupted pixels (detection statistics).
English abstract
Keywords
adaptive median filter, image processing, FPGA,
Key words in English
Authors
RIV year
2010
Released
17.04.2008
Publisher
IEEE Computer Society
Location
Bratislava
ISBN
978-1-4244-2276-0
Book
Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Pages from
110
Pages to
115
Pages count
6
URL
https://www.fit.vut.cz/research/publication/8604/
BibTex
@inproceedings{BUT27767, author="Zdeněk {Vašíček} and Lukáš {Sekanina}", title="Novel Hardware Implementation of Adaptive Median Filters", booktitle="Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop", year="2008", pages="110--115", publisher="IEEE Computer Society", address="Bratislava", doi="10.1109/ddecs.2008.4538766", isbn="978-1-4244-2276-0", url="https://www.fit.vut.cz/research/publication/8604/" }
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