RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool

Paper in proceedings outside WoS and Scopus

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

The paper presents testability analysis method which is based on partitioning circuit under analysis (CUA) to testable blocks (TBs). A formal approach utilizing the concepts of discrete mathematics is used for this purpose. The partitioning CUA into TBs is further exploited for power consumption optimization during test application. Software tools which were developed during the research and integrated into the third party design tool are also described. Experimental results gained from applying the methodology on selected benchmarks and practical designs are demonstrated.

Testable block, power consumption estimation, test vectors generation, power consumption optimization.

Testable block, power consumption estimation, test vectors generation, power consumption optimization.

ŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z.

12.10.2007

Institute of Computing Technology, Chinese Academy of Sciences

Beijing

IEEE 8th Workshop on RTL and High Level Testing

175

181

7

https://www.fit.vut.cz/research/publication/8487/

wrtlt07