Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals

Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals

Paper in proceedings (conference paper)

The paper describes VHDL-AMS simulation model of a digital link (with a signal source) together with "software" clock and data recovery module [1] and common recovery circuit incorporating a PLL. Performance of both methods is compared and discussed. Models were created to help to improve the software recovery method. All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS [2] models of signal source, data path and recovery circuits. The soft-ware recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

The paper describes VHDL-AMS simulation model of a digital link (with a signal source) together with "software" clock and data recovery module [1] and common recovery circuit incorporating a PLL. Performance of both methods is compared and discussed. Models were created to help to improve the software recovery method. All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS [2] models of signal source, data path and recovery circuits. The soft-ware recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

Simulation, VHDL-AMS, Clock and data recovery, SystemVision

Simulation, VHDL-AMS, Clock and data recovery, SystemVision

KUBÍČEK, M.

01.01.2007

Ing. Zdeněk Novotný CSc., Ondráčková 105, Brno

Vysoké učení technické v Brně

978-80-214-3410-3

Proceedings of the 13th Conference Student EEICT 2007

266

270

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