Publication result detail

Formal Model of Testable Block

HERRMAN, T.

Original Title

Formal Model of Testable Block

English Title

Formal Model of Testable Block

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

English abstract

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

Keywords

RT level, Testable block, formal model, scan chain

Key words in English

RT level, Testable block, formal model, scan chain

Authors

HERRMAN, T.

Released

27.04.2006

Publisher

Faculty of Electrical Engineering and Communication BUT

Location

Brno

ISBN

80-214-3163-6

Book

Proceedings of 12th Conference Student EEICT 2006, Volume 4

Pages from

451

Pages to

455

Pages count

5

URL

https://www.fit.vut.cz/research/publication/8051/

BibTex

@inproceedings{BUT22191,
  author="Tomáš {Herrman}",
  title="Formal Model of Testable Block",
  booktitle="Proceedings of 12th Conference Student EEICT 2006, Volume 4",
  year="2006",
  pages="451--455",
  publisher="Faculty of Electrical Engineering and Communication BUT",
  address="Brno",
  isbn="80-214-3163-6",
  url="https://www.fit.vut.cz/research/publication/8051/"
}

Documents

Formální model testovatelného bloku - článek