Publication result detail

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

BRADÁČ, Z., VALACH, S.

Original Title

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

English Title

10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS

Type

Paper in proceedings (conference paper)

Original Abstract

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

English abstract

The present electronic industry achieves unusual expansion of communication technology based on high-speed serial interfaces. It is due to need higher bandwidth and performance, lower size, power consumption and device price. The article will be focused on a different approaches how to implement 10 GigaBit Ethernet physical layer in the FPGA based structures.

Key words in English

FPGA, Ethernet, XGMII, XAUI, RocketIO, Combo6.

Authors

BRADÁČ, Z., VALACH, S.

Released

01.02.2006

Publisher

VUT Brno

Location

Brno

ISBN

80-214-3130-X

Book

Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003

Pages from

427

Pages count

6

BibTex

@inproceedings{BUT19451,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="10G BIT ETHERNET PHY IMPLEMENTATION IN FPGA BASED SYSTEMS",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  year="2006",
  pages="6",
  publisher="VUT Brno",
  address="Brno",
  isbn="80-214-3130-X"
}