Publication result detail

Hardware Acceleration of Algorithms in Computer Networks using FPGA

KOŘENEK, J.

Original Title

Hardware Acceleration of Algorithms in Computer Networks using FPGA

English Title

Hardware Acceleration of Algorithms in Computer Networks using FPGA

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

With the growing speed of computer networks, network devices need more processing power to achieve wire speed throughput. As current processor have limited performance, routers and other network devices use hardware acceleration to achieve wire speed throughput with reasonable power consumption. Usually, the throughput is decreased by time critical operations which has to be performed for every packet or every byte of network traffic. The presentation will be focused on hardware acceleration of time critical operations in networking using FPGA and provides results of recent research in longest prefix matching (IP look-up), packet classification and regular expressions matching. The end of the presentation will be devoted to the rapid development of hardware accelerated network applications.

English abstract

With the growing speed of computer networks, network devices need more processing power to achieve wire speed throughput. As current processor have limited performance, routers and other network devices use hardware acceleration to achieve wire speed throughput with reasonable power consumption. Usually, the throughput is decreased by time critical operations which has to be performed for every packet or every byte of network traffic. The presentation will be focused on hardware acceleration of time critical operations in networking using FPGA and provides results of recent research in longest prefix matching (IP look-up), packet classification and regular expressions matching. The end of the presentation will be devoted to the rapid development of hardware accelerated network applications.

Keywords

hardware acceleration, FPGA, computer networks

Key words in English

hardware acceleration, FPGA, computer networks

Authors

KOŘENEK, J.

Released

15.08.2013

Publisher

IEEE Computer Society

Location

Brno

ISBN

978-1-4673-6133-0

Book

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Pages from

11

Pages to

11

Pages count

1

BibTex

@inproceedings{BUT192917,
  author="Jan {Kořenek}",
  title="Hardware Acceleration of Algorithms in Computer Networks using FPGA",
  booktitle="2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  year="2013",
  pages="11--11",
  publisher="IEEE Computer Society",
  address="Brno",
  isbn="978-1-4673-6133-0"
}