Detail publikačního výsledku

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

HÁZE, J.; VRBA, R.; FUJCIK, L.; SAJDL, O.

Original Title

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

English Title

Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration

Type

Paper in proceedings (conference paper)

Original Abstract

The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational amplifier (op-amp) sharing technique, shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as mentioned above.

English abstract

The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational amplifier (op-amp) sharing technique, shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as mentioned above.

Keywords

Pipelined ADC, switched-capacitors, background calibration, portable devices

Key words in English

Pipelined ADC, switched-capacitors, background calibration, portable devices

Authors

HÁZE, J.; VRBA, R.; FUJCIK, L.; SAJDL, O.

Released

01.01.2006

Publisher

IEEE

Location

Mauritius

ISBN

0-7695-2552-0

Book

Proceedings of ICN 2006, ICONS 2006, MCL 2006

Pages from

116

Pages count

6

Full text in the Digital Library

http://hdl.handle.net/

BibTex

@inproceedings{BUT18357,
  author="Jiří {Háze} and Radimír {Vrba} and Lukáš {Fujcik} and Ondřej {Sajdl}",
  title="Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration",
  booktitle="Proceedings of ICN 2006, ICONS 2006, MCL 2006",
  year="2006",
  number="1",
  pages="6",
  publisher="IEEE",
  address="Mauritius",
  isbn="0-7695-2552-0"
}