Publication detail

Optimizing Packet Classification on FPGA

KEKELY, M. KOŘENEK, J.

Original Title

Optimizing Packet Classification on FPGA

Type

conference paper

Language

English

Original Abstract

Packet classification is a crucial time-critical operation for many different networking tasks ranging from switching or routing to monitoring and security devices like firewalls or IDS. Accelerated architectures implementing packet classification must satisfy the ever-growing demand for current high-speed networks. However, packet classification is generally used together with other packet processing algorithms, which decreases the available hardware resources on the FPGA chip. The introduction of the P4 language requires the packet classification to be even more flexible while maintaining a high throughput with limited resources. Thus, we need flexible and high-performance architectures to balance processing speed and hardware resources for specific types of rules. DCFL algorithm provides high performance and flexibility. Therefore, we propose optimizations to the DCFL algorithm and overall packet processing hardware architecture. The goal is to maximize the throughput and minimize the resource strain. The main idea of the approach is to analyze the ruleset, identify some conflicting rules and offload these rules to other hardware modules. This approach allows us to process packets faster, even in the worst-case scenarios. Moreover, we can fit more packet processing into the FPGA and fine-tune the packet processing architecture to meet a specific network application's throughput and resource demands. With the proposed optimizations we can achieve up to a 76 % increase in the throughput of the packet classification. Alternatively, we can achieve up to a 37 % decrease in resources needed.

Keywords

FPGA, packet classification, DCFL, optimization

Authors

KEKELY, M.; KOŘENEK, J.

Released

3. 5. 2023

Publisher

Institute of Electrical and Electronics Engineers

Location

Tallinn

ISBN

979-8-3503-3277-3

Book

PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

ISBN

2334-3133

Periodical

IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

State

United States of America

Pages from

7

Pages to

12

Pages count

6

URL

https://ieeexplore.ieee.org/document/10139668

BibTex

@inproceedings{BUT183418,
  author="Michal {Kekely} and Jan {Kořenek}",
  title="Optimizing Packet Classification on FPGA",
  booktitle="PROCEEDINGS 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)",
  year="2023",
  journal="IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems",
  pages="7--12",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Tallinn",
  doi="10.1109/DDECS57882.2023.10139668",
  isbn="979-8-3503-3277-3",
  issn="2334-3133",
  url="https://ieeexplore.ieee.org/document/10139668"
}