Detail publikačního výsledku

Partial Scan Methodologoies

KOTÁSEK, Z.

Original Title

Partial Scan Methodologoies

English Title

Partial Scan Methodologoies

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

Partial scan methodologies are seen as an alternative to applying atest to a digital circuit. In the presentation a survey of themethodologies is given.

English abstract

Partial scan methodologies are seen as an alternative to applying atest to a digital circuit. In the presentation a survey of themethodologies is given.

Keywords

digital circuit testability, test application

Key words in English

digital circuit testability, test application

Authors

KOTÁSEK, Z.

Released

18.04.2004

Publisher

Slovak Academy of Science

Location

Bratislava

Book

Research and Training Action for System on Chip Design, 5th FP Project

Pages from

1

Pages to

77

Pages count

77

Full text in the Digital Library

http://hdl.handle.net/

BibTex

@inproceedings{BUT17574,
  author="Zdeněk {Kotásek}",
  title="Partial Scan Methodologoies",
  booktitle="Research and Training Action for System on Chip Design, 5th FP Project",
  year="2004",
  pages="1--77",
  publisher="Slovak Academy of Science",
  address="Bratislava"
}