Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

Paper in proceedings (conference paper)

In July 2020, the lattice-based CRYSTALS-Dilithium digital signature scheme has been chosen as one of the three third-round finalists in the post-quantum cryptography standardization process by the National Institute of Standards and Technology (NIST). In this work, we present the first Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of the CRYSTALS-Dilithium signature scheme for Field-Programmable Gate Arrays (FPGAs). Due to our parallelization-based design requiring only low numbers of cycles, running at high frequency and using reasonable amount of hardware resources on FPGA, our implementation is able to sign 15832 messages per second and verify 10524 signatures per second. In particular, the signing algorithm requires 68461 Look-Up Tables (LUTs), 86295 Flip-Flops (FFs), and the verification algorithm takes 61738 LUTs and 34963 FFs on Virtex 7 UltraScale+ FPGAs. In this article, experimental results for each Dilithium security level are provided and our VHDL-based implementation is compared with related High-Level Synthesis (HLS)-based implementations. Our solution is ca 114 times faster (in the signing algorithm) and requires less hardware resources.

In July 2020, the lattice-based CRYSTALS-Dilithium digital signature scheme has been chosen as one of the three third-round finalists in the post-quantum cryptography standardization process by the National Institute of Standards and Technology (NIST). In this work, we present the first Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of the CRYSTALS-Dilithium signature scheme for Field-Programmable Gate Arrays (FPGAs). Due to our parallelization-based design requiring only low numbers of cycles, running at high frequency and using reasonable amount of hardware resources on FPGA, our implementation is able to sign 15832 messages per second and verify 10524 signatures per second. In particular, the signing algorithm requires 68461 Look-Up Tables (LUTs), 86295 Flip-Flops (FFs), and the verification algorithm takes 61738 LUTs and 34963 FFs on Virtex 7 UltraScale+ FPGAs. In this article, experimental results for each Dilithium security level are provided and our VHDL-based implementation is compared with related High-Level Synthesis (HLS)-based implementations. Our solution is ca 114 times faster (in the signing algorithm) and requires less hardware resources.

Post-quantum cryptography;Lattice-based cryptography;Digital signatures;Number-theoretic transform;FPGA; VHDL implementation;Parallelization;Optimization;

Post-quantum cryptography;Lattice-based cryptography;Digital signatures;Number-theoretic transform;FPGA; VHDL implementation;Parallelization;Optimization;

RICCI, S.; MALINA, L.; JEDLIČKA, P.; SMÉKAL, D.; HAJNÝ, J.; CÍBIK, P.; DZURENDA, P.; DOBIÁŠ, P.

2022

18.08.2021

978-1-4503-9051-4

ARES 2021: The 16th International Conference on Availability, Reliability and Security

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https://dl.acm.org/doi/10.1145/3465481.3465756

http://hdl.handle.net/