Publication result detail

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z.; TUPEC, P.

Original Title

New approach to the FPGA testing based on the Boundary Scan

English Title

New approach to the FPGA testing based on the Boundary Scan

Type

Paper in proceedings outside WoS and Scopus

Original Abstract

In the paper, a method enabling to verify the functionality of an FPGAdesign is presented. This method is based on the formal modelconstruction of the register transfer (RT) level digital circuit. Thisnew approach allows FPGA designers to debug and verify their hardwarebeing developed. A Boundary scan is used as a communication interface.As an input, a digital circuit structure at RT level designed using anyDfT technique is assumed.

English abstract

In the paper, a method enabling to verify the functionality of an FPGAdesign is presented. This method is based on the formal modelconstruction of the register transfer (RT) level digital circuit. Thisnew approach allows FPGA designers to debug and verify their hardwarebeing developed. A Boundary scan is used as a communication interface.As an input, a digital circuit structure at RT level designed using anyDfT technique is assumed.

Keywords

JTAG, debugger, RT level, boundary scan

Key words in English

JTAG, debugger, RT level, boundary scan

Authors

KOTÁSEK, Z.; TUPEC, P.

RIV year

2011

Released

11.05.2004

Publisher

Marq software s.r.o.

Location

Ostrava

ISBN

80-85988-98-4

Book

Proceedings of 38th International Conference MOSIS'04

Pages from

120

Pages to

123

Pages count

4

BibTex

@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  year="2004",
  pages="120--123",
  publisher="Marq software s.r.o.",
  address="Ostrava",
  isbn="80-85988-98-4"
}