Publication detail

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z., TUPEC, P.

Original Title

New approach to the FPGA testing based on the Boundary Scan

Type

conference paper

Language

English

Original Abstract

In the paper, a method enabling to verify the functionality of an FPGA design is presented. This method is based on the formal model construction of the register transfer (RT) level digital circuit. This new approach allows FPGA designers to debug and verify their hardware being developed. A Boundary scan is used as a communication interface. As an input, a digital circuit structure at RT level designed using any DfT technique is assumed.

Keywords

JTAG, debugger, RT level, boundary scan

Authors

KOTÁSEK, Z., TUPEC, P.

RIV year

2004

Released

11. 5. 2004

Location

Ostrava

ISBN

80-85988-98-4

Book

Proceedings of 38th International Conference MOSIS'04

Pages from

120

Pages to

123

Pages count

4

BibTex

@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  year="2004",
  pages="120--123",
  address="Ostrava",
  isbn="80-85988-98-4"
}