Publication result detail

Versatile Chirp Sine Generator on Fix-point FPGA

KUNZ, J.; BENEŠ, P.

Original Title

Versatile Chirp Sine Generator on Fix-point FPGA

English Title

Versatile Chirp Sine Generator on Fix-point FPGA

Type

WoS Article

Original Abstract

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

English abstract

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

Keywords

Linear Chirp Sine, Logarithm Chirp Sine, FPGA, Fix-point, Generation

Key words in English

Linear Chirp Sine, Logarithm Chirp Sine, FPGA, Fix-point, Generation

Authors

KUNZ, J.; BENEŠ, P.

RIV year

2021

Released

31.12.2020

Publisher

Czech Technical University in Prague

Location

Prague

ISBN

1805-2363

Periodical

Acta Polytechnica

Volume

60

Number

6

State

Czech Republic

Pages from

462

Pages to

468

Pages count

7

URL

https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049

Full text in the Digital Library

http://hdl.handle.net/11012/196548

BibTex

@article{BUT160854,
  author="Jan {Kunz} and Petr {Beneš}",
  title="Versatile Chirp Sine Generator on Fix-point FPGA",
  journal="Acta Polytechnica",
  year="2020",
  volume="60",
  number="6",
  pages="462--468",
  doi="10.14311/AP.2020.60.0462",
  issn="1210-2709",
  url="https://ojs.cvut.cz/ojs/index.php/ap/article/view/6049"
}

Documents

6049-Article Text-22260-1-10-20210112