Publication detail

Input and Output Generation for the Verification of ALU: a Use Case

ČEKAN, O. PÁNEK, R. KOTÁSEK, Z.

Original Title

Input and Output Generation for the Verification of ALU: a Use Case

Type

conference paper

Language

English

Original Abstract

The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.

Keywords

Stimuli generation, arithmetic logic unit, probabilistic constrained grammar, functional verification

Authors

ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z.

Released

14. 9. 2018

Publisher

IEEE Computer Society

Location

Kazan

ISBN

978-1-5386-5710-2

Book

Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018

Pages from

331

Pages to

336

Pages count

6

URL

https://www.fit.vut.cz/research/publication/11833/

BibTex

@inproceedings{BUT155097,
  author="Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}",
  title="Input and Output Generation for the Verification of ALU: a Use Case",
  booktitle="Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018",
  year="2018",
  pages="331--336",
  publisher="IEEE Computer Society",
  address="Kazan",
  doi="10.1109/EWDTS.2018.8524641",
  isbn="978-1-5386-5710-2",
  url="https://www.fit.vut.cz/research/publication/11833/"
}