Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

WoS Article

Approximate computing exploits the fact that many applicationsare inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employedin these applications. However, most current approximate multipliersare based on ad-hoc circuit structures and, for automated circuitapproximation methods, large efficient designs are difficult to find dueto the increased search space. Moreover, existing design methods do nottypically provide sufficient formal guarantees in terms of error if largeapproximate multipliers are constructed. To address these challenges,this brief introduces a general and efficient method for constructinglarge high-quality approximate multipliers with respect to the objectivesformulated in terms of the power-delay product and a provable errorbound. This is demonstrated by means of a comparative evaluation ofapproximate 16-bit multipliers constructed by the proposed method andother methods in the literature.

Approximate computing exploits the fact that many applicationsare inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employedin these applications. However, most current approximate multipliersare based on ad-hoc circuit structures and, for automated circuitapproximation methods, large efficient designs are difficult to find dueto the increased search space. Moreover, existing design methods do nottypically provide sufficient formal guarantees in terms of error if largeapproximate multipliers are constructed. To address these challenges,this brief introduces a general and efficient method for constructinglarge high-quality approximate multipliers with respect to the objectivesformulated in terms of the power-delay product and a provable errorbound. This is demonstrated by means of a comparative evaluation ofapproximate 16-bit multipliers constructed by the proposed method andother methods in the literature.

Approximate computing circuits and systems,circuit synthesis, circuits, computers and informationprocessing

Approximate computing circuits and systems,circuit synthesis, circuits, computers and informationprocessing

MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; JIANG, H.; HAN, J.

2019

01.11.2018

1063-8210

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

26

11

United States of America

2572

2576

5

https://www.fit.vut.cz/research/publication/11678/

08423431