Publication detail

Hardware-Accelerated Twofish Core for FPGA

SMÉKAL, D. HAJNÝ, J. MARTINÁSEK, Z.

Original Title

Hardware-Accelerated Twofish Core for FPGA

Type

conference paper

Language

English

Original Abstract

This article describes the hardware-accelerated implementation of the Twofish encryption algorithm on Field Programmable Gate Array (FPGA) network cards. The encryption core was implemented using the Virtex 7 network card to achieve real-time encryption and decryption. The algorithm was implemented for 128-bit words and 128-bit keys. This article demonstrates that the Twofish encryption core can operate with the maximum clock frequencies of 315MHz and achieves the throughput of 48 Gbps, which is faster than most currently implemented systems.

Keywords

Twofish; Encryption; Decryption; Hardware-Accelerated; FPGA; Component; VHDL; Core; Virtex-7

Authors

SMÉKAL, D.; HAJNÝ, J.; MARTINÁSEK, Z.

Released

4. 7. 2018

Location

Atény, Řecko

ISBN

978-1-5386-4695-3

Book

2018 41st International Conference on Telecommunications and Signal Processing (TSP)

ISBN

1805-5435

Periodical

International Conference on Telecommunications and Signal Processing (TSP)

State

Czech Republic

Pages from

338

Pages to

341

Pages count

836

URL

http://tsp.vutbr.cz/datas/tsp2018_proc/TSP2018.pdf

BibTex

@inproceedings{BUT148926,
  author="David {Smékal} and Jan {Hajný} and Zdeněk {Martinásek}",
  title="Hardware-Accelerated Twofish Core for FPGA",
  booktitle="2018 41st International Conference on Telecommunications and Signal Processing (TSP)",
  year="2018",
  journal="International Conference on Telecommunications and Signal Processing (TSP)",
  pages="338--341",
  address="Atény, Řecko",
  doi="10.1109/TSP.2018.8441386",
  isbn="978-1-5386-4695-3",
  issn="1805-5435",
  url="http://tsp.vutbr.cz/datas/tsp2018_proc/TSP2018.pdf"
}